The increase in the integration density and the speed of integrated circuits is leading to a continuous reduction in the size of the elementary transistors of which they are composed. Indeed, the development of fabrication technologies is, in particular, characterized by a reduction in the lateral dimensions which is taking place more quickly over time than that of the vertical dimensions (for example the minimum widths of the photolithographically etched patterns are being reduced at a faster rate than the typical thicknesses of the deposited layers). In certain cases, this results in a significant increase in the form factors (depth/width ratio of a pattern) in comparison with previous-generation technologies, and therefore in a tortuous relief.
Furthermore, deposits made on non-planar surfaces of this type are involved in certain fabrication steps for integrated circuits. Among these, mention may be made of the side insulation techniques which require the deposition of one or more dielectric layers in trenches etched into the silicon, as well as intermetallic insulation techniques.
On account of the tortuous relief of the surface which receives the deposit, morphological defects may appear in these deposited layers. Mention may, principally, be made of cavity effects, crackling effects and wave effects (periodic or pseudo-periodic variations in the thickness over large distances).
It is therefore expedient to find deposition processes which overcome these drawbacks that are connected, in particular, with the geometry of the underlying patterns and the inherent physical characteristics of the materials that are deposited.